1. Field of the Invention
The present invention relates to a lead frame, in particular to a plated lead frame for use in semiconductor devices.
2. Description of Related Art
According to reduction in size and weight of small products in recent years, there is a growing demand for reduction in size and thickness of semiconductor devices. Printed circuit boards for implementing the semiconductor devices are also required to be thin, small and multilayered. In general, the semiconductor device is implemented on the printed circuit board by reflowing.
Hereinafter, explanation of problems involved in the step of reflowing the semiconductor device in a conventional manner is provided with reference to the drawings.
FIGS. 9A, 9B and 9C show how a semiconductor device is implemented on a board. Here, a semiconductor device 32 is prepared by mounting a semiconductor element on a lead frame and sealing it into a package with a mold resin 33.
First, in a solder printing step shown in FIG. 9A, solder paste 31 is applied onto electrode pads (not shown) provided on a printed circuit board (wiring board) 30. Then, in a mounting step shown in FIG. 9B, the semiconductor device 32 is mounted on the printed circuit board 30. Then, in a reflowing step shown in FIG. 9C, the whole device including the printed circuit board 30 and the semiconductor device 32 is heated at a high temperature to melt the solder paste 31. The solder paste 31 is then cooled, thereby fixing and connecting the semiconductor device 32 to the print circuit board 30.
Through these steps, outer leads 34 electrically conducted with electrode pads in the semiconductor element are electrically connected to the printed circuit board 30 via the solder paste 31. The bottommost surface of each of the outer leads 34 of the semiconductor device 32 is generally called a mounting surface 35. The outer leads 34 are configured such that coplanarity 36 indicating flatness of the mounting surface 35 as shown in FIG. 10 is in the range of several tens of μm.
In the reflowing step, the semiconductor device and the printed circuit board are deformed by various loads applied thereto while the temperature rises from a normal temperature of about 25° C. to a high temperature of about 250° C. Specifically, the semiconductor device 32 is deformed due to the difference in thermal expansion coefficient between the outer leads 34 principally made of iron or copper and the mold resin 33. If the coplanarity 36 is high, the outer leads 34 are deformed to be lifted above the printed circuit board 30.
The printed circuit board 30 which is made thin or multilayered is also deformed under the high temperature during the reflowing step. The deformation of these components synergistically causes defects, even if the mounting surfaces 35 of the outer leads 34 are in contact with the solder paste 31. For example, the solder paste 31 does not achieve good wicking, i.e., solder fillet is not formed, or alternatively, the outer leads 34 are lifted above the solder paste 31 to fail to establish electrical connection, thereby leading to solder joint open failure.
In order to prevent such defects, the surface of the lead frame is plated to improve wettability between the outer leads 34 and the solder paste 31.
In recent years, from the aspect of environment issues, lead free solder paste, such as SnAgCu, SnZn and SnAgBiIn, are used as the solder paste 31 in many cases. However, the lead free solder pastes are poorer in wettability than conventional Sn-37% Pb eutectic solder and are likely to cause the defects such as the failure in solder fillet formation and the solder joint open failure. Therefore, a plating having good wettability with the lead free solder paste is required.
When the outer leads 34 are coated with a SnPb eutectic plating having a relatively low melting point, the plating itself is molten under the high temperature condition during the reflowing step. Therefore, even if the lead free solder paste is used, the defect derived from the solder paste's lack of good wicking characteristics is less likely to occur. However, from the environmental standpoint, use of the Pb-containing plating will be restricted only in some very limited locations in electronic products. Thus, the plating of this kind is not available for general use.
When a lead free plating is used, e.g., a SnBi plating (a two-layer plating including a tin layer and a 2% Bi layer formed thereon), the SnBi plating itself is molten due to its low melting point just like the SnPb eutectic plating. Therefore, the problem of the solder paste's lack of good wicking characteristics does not occur.
Further, when a palladium-based metallic plating which has been adopted as a lead free plating by many manufacturers is used (e.g., a three-layer plating of nickel 20/palladium 24/gold 28 as shown in FIG. 11), the palladium-based metallic plating is not molten because its melting point is much higher than the high temperature condition during the reflowing step. However, the failure in solder fillet formation and the solder joint open failure have been less likely to occur even if the lead free solder paste is used. It is because the outer leads have been arranged at a pitch of 0.6 mm or more (e.g., see Japanese Unexamined Patent Publication H4-115558).